Epitaxially Thickened Doped or Undoped Core Nanowire FET Structure and Method for Increasing Effective Device Width

ABSTRACT

Techniques for increasing effective device width of a nanowire FET device are provided. In one aspect, a method of fabricating a FET device is provided. The method includes the following steps. A SOI wafer is provided having an SOI layer over a BOX. Nanowire cores and pads are etched in the SOI layer in a ladder-like configuration. The nanowire cores are suspended over the BOX. Epitaxial shells are formed surrounding each of the nanowire cores. A gate stack is formed that surrounds at least a portion of each of the nanowire cores/epitaxial shells, wherein the portions of the nanowire cores/epitaxial shells surrounded by the gate stack serve as channels of the device, and wherein the pads and portions of the nanowire cores/epitaxial shells that extend out from the gate stack serve as source and drain regions of the device.

FIELD OF THE INVENTION

The present invention relates to nanowire field effect transistor (FET)devices and more particularly, to techniques for increasing effectivedevice width of a nanowire FET device by forming a doped or undopedepitaxial shell around a doped or undoped nanowire core.

BACKGROUND OF THE INVENTION

As scaling conventional planar complementary metal-oxide semiconductor(CMOS) becomes increasingly challenging, several non-planar devicestructures have been considered. One such non-planar device structure isa gate all around field effect transistor (FET). A gate all around FETachieves superior short channel characteristics from the electrostaticsthat the geometry of the structure provides. In fact, in some situationsthere is actually overscaling (i.e., better electrostatics thanrequired).

However, one issue with gate all around FETs is in maintaining effectivedevice width scaling after the various nanowire formation processes. Onesolution to this problem is to create stacked layered structures. Tocreate layered structures, however, creates additional processcomplexities. Another solution is to pattern large nanowires which, aspatterned, have a small spacing between the nanowires. Such a patterningprocess, however, is very difficult to control and to produce a reliableyield.

Therefore, techniques for maintaining desired device width in processflows that involve nanowire thinning would be desirable.

SUMMARY OF THE INVENTION

The present invention provides techniques for increasing effectivedevice width of a nanowire field effect transistor (FET) device byforming a doped or undoped epitaxial shell around a doped or undopednanowire core. In one aspect of the invention, a method of fabricating aFET device is provided. The method includes the following steps. Asemiconductor-on-insulator (SOI) wafer is provided having an SOI layerover a buried oxide (BOX). Nanowire cores and pads are etched in the SOIlayer, wherein the pads are attached at opposite ends of the nanowirecores in a ladder-like configuration. The nanowire cores are suspendedover the BOX. The nanowire cores may optionally be thinned (e.g., priorto the growth of the epitaxial shell to allow for varying ratio ofcore-to-shell thickness). Epitaxial shells are formed surrounding eachof the nanowire cores. A gate stack is formed that surrounds at least aportion of each of the nanowire cores and the epitaxial shells, whereinthe portions of the nanowire cores and the epitaxial shells surroundedby the gate stack serve as channels of the device, and wherein the padsand portions of the nanowire cores and the epitaxial shells that extendout from the gate stack serve as source and drain regions of the device.

In another aspect of the invention, a FET device is provided. The FETdevice includes a wafer having a BOX; nanowire cores and pads attachedat opposite ends of the nanowire cores in a ladder-like configuration onthe BOX, wherein the nanowire cores are suspended over the BOX;epitaxial shells surrounding each of the nanowire cores; and a gatestack that surrounds at least a portion of each of the nanowire coresand the epitaxial shells, wherein the portions of the nanowire cores andthe epitaxial shells surrounded by the gate stack serve as channels ofthe device, and wherein the pads and portions of the nanowire cores andthe epitaxial shells that extend out from the gate stack serve as sourceand drain regions of the device.

In yet another aspect of the invention, a method of fabricating a FETdevice is provided. The method includes the following steps. A SOI waferis provided having an SOI layer over a BOX, wherein the SOI layer ispresent between a buried nitride layer beneath the SOI layer and anitride cap above the SOI layer. The SOI layer, the buried nitride layerand the nitride cap are etched to form nanowire cores and pads in theSOI layer, wherein the pads are attached at opposite ends of thenanowire cores in a ladder-like configuration, wherein the buriednitride layer is present beneath each of the nanowire cores and thenitride cap is present on top of each of the nanowire cores, and whereinsidewalls of the nanowire cores are exposed. The nanowire cores aresuspended over the BOX. Epitaxial sidewalls are formed over thesidewalls of the nanowires cores. The buried nitride layer and thenitride cap are removed from the nanowire cores. A gate stack is formedthat surrounds at least a portion of each of the nanowire cores and theepitaxial sidewalls, wherein the portions of the nanowire cores and theepitaxial sidewalls surrounded by the gate stack serve as channels ofthe device, wherein the pads and portions of the nanowire cores and theepitaxial sidewalls that extend out from the gate stack serve as sourceand drain regions of the device.

In still yet another aspect of the invention, a FET device is provided.The FET device includes a wafer having a BOX; nanowire cores and padsattached at opposite ends of the nanowire cores in a ladder-likeconfiguration on the BOX, wherein the nanowire cores are suspended overthe BOX; epitaxial sidewall covering sidewalls of the nanowire cores andwhich extend along each of the nanowire cores in a plane parallel to theBOX; and a gate stack that surrounds at least a portion of each of thenanowire cores and the epitaxial sidewalls, wherein the portions of thenanowire cores and the epitaxial sidewalls surrounded by the gate stackserve as channels of the device, wherein the pads and portions of thenanowire cores and the epitaxial sidewalls that extend out from the gatestack serve as source and drain regions of the device.

A more complete understanding of the present invention, as well asfurther features and advantages of the present invention, will beobtained by reference to the following detailed description anddrawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a three-dimensional diagram illustrating asemiconductor-on-insulator (SOI) wafer having a SOI layer over a buriedoxide (BOX) which is a starting platform for fabrication of a nanowirefield effect transistor (FET) device according to an embodiment of thepresent invention;

FIG. 2 is a three-dimensional diagram illustrating a nanowire hardmaskhaving been formed on the SOI layer according to an embodiment of thepresent invention;

FIG. 3 is a three-dimensional diagram illustrating the hardmask havingbeen used to pattern nanowire cores and pads in the SOI layer and thehardmask having been removed according to an embodiment of the presentinvention;

FIG. 4 is a three-dimensional diagram illustrating the nanowire coreshaving been suspended over the BOX by undercutting the BOX beneath thenanowires, and the nanowire cores having been smoothed according to anembodiment of the present invention;

FIG. 5 is a three-dimensional diagram illustrating the nanowire coreshaving been thinned according to an embodiment of the present invention;

FIG. 6 is a three-dimensional diagram illustrating an epitaxial materialhaving been formed on the nanowire cores (as a shell) and also on thepads according to an embodiment of the present invention;

FIG. 7 is a three-dimensional diagram illustrating a gate stack havingbeen formed surrounding the nanowire cores/epitaxial shells in a gateall around configuration according to an embodiment of the presentinvention;

FIG. 8 is a cross-sectional diagram illustrating a cut through a portionof the gate stack according to an embodiment of the present invention;

FIG. 9 is a three-dimensional diagram illustrating spacers having beenformed on opposite sides of the gate stack according to an embodiment ofthe present invention;

FIG. 10 is a three-dimensional diagram illustrating a contact materialhaving been formed on the exposed epitaxial material according to anembodiment of the present invention;

FIG. 11 is a schematic diagram illustrating effective device width,spacing between adjacent channels (channel-to-channel spacing) andchannel pitch, and how by way of the present techniques, the devicewidth is increased thereby decreasing the channel-to-channel spacingaccording to an embodiment of the present invention;

FIG. 12A is a cross-sectional diagram illustrating a starting wafer foran exemplary alternative process flow having an SOI layer (sandwichedbetween a buried nitride layer and a nitride cap) over a BOX accordingto an embodiment of the present invention;

FIG. 12B is a top-down diagram of the structure of FIG. 12A according toan embodiment of the present invention;

FIG. 13A is a cross-sectional diagram illustrating nanowire cores (whichhave been formed in the SOI layer) having been suspended by recessing aportion of the BOX beneath the nanowire cores according to an embodimentof the present invention;

FIG. 13B is a top-down diagram of the structure of FIG. 13A according toan embodiment of the present invention;

FIG. 14A is a cross-sectional diagram illustrating another perspectiveof the suspended nanowire cores which illustrates how sidewalls of thesuspended nanowire cores are exposed while top and bottom surfaces ofthe suspended nanowire cores are covered by the top the nitride cap andthe buried nitride layer according to an embodiment of the presentinvention;

FIG. 14B is a top-down diagram of the structure of FIG. 14A according toan embodiment of the present invention;

FIG. 15A is a cross-sectional diagram illustrating selective epitaxyhaving been used to add epitaxial sidewalls over exposed sidewallsurfaces of the suspended nanowire cores according to an embodiment ofthe present invention;

FIG. 15B is a top-down diagram of the structure of FIG. 15A according toan embodiment of the present invention;

FIG. 16A is a cross-sectional diagram illustrating the top nitride capand the buried nitride layer having been removed from the suspendednanowire cores by a selective etch according to an embodiment of thepresent invention;

FIG. 16B is a top-down diagram of the structure of FIG. 16A according toan embodiment of the present invention; and

FIG. 17 is a cross-sectional diagram illustrating a gate stack havingbeen formed surrounding the suspended nanowire cores according to anembodiment of the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Provided herein are techniques for maintaining effective device widthscaling in gate all around nanowire field effect transistor (FET)devices following nanowire thinning by growing a doped or undopedepitaxial shell around either a doped or undoped core device. Thepresent techniques will now be described by way of reference to FIGS.1-10 which illustrate an exemplary nanowire FET device fabricationprocess flow.

The fabrication process begins with a semiconductor-on-insulator (SOI)wafer. See FIG. 1. An SOI wafer typically includes a layer of asemiconductor material (also commonly referred to as asemiconductor-on-insulator layer or SOI layer) separated from asubstrate by an insulator. When the insulator is an oxide (e.g., silicondioxide (SiO₂)), it is commonly referred to as a buried oxide, or BOX.According to the present techniques, the SOI layer will serve as anactive layer of the device in which nanowire cores and pads will bepatterned (see below).

In the example shown in FIG. 1, the starting wafer includes an SOI layer104 over a BOX 102. For ease of depiction, a substrate typically locatedbelow the BOX 102, is not shown. According to an exemplary embodiment,SOI layer 104 is formed from a semiconducting material, such as silicon(Si) (e.g., single-crystalline silicon), silicon germanium (SiGe) orsilicon carbon (SiC). Thus, the SOI layer 104 may also be referred to asa “semiconductor device layer” or simply as a “semiconductor layer.”

According to an exemplary embodiment, SOI layer 104 preferably has athickness of from about 5 nanometers (nm) to about 40 nm. Commerciallyavailable SOI wafers typically have a thicker SOI layer. Thus, the SOIlayer of a commercial wafer can be thinned using techniques such asoxidative thinning to achieve the desired active layer thickness for thepresent techniques.

Optionally, the SOI layer 104 may be doped such that when nanowire coresare patterned in the SOI layer 104, the cores will likewise be doped.This step is optional, since it may be desirable to leave the nanowirecores undoped.

Thus in some embodiments, a p-type or n-type dopant may be used to dopethe SOI layer 104. By way of example only, if the device being producedis an n-channel nanowire FET, then it may be desirable to implant ap-type dopant into the SOI layer 104 (resulting in p-doped nanowirecores, see below). Suitable p-type dopants include, but are not limitedto, boron. Alternatively, when the device being produced is a p-channelnanowire FET, then it may be desirable to implant an n-type dopant intothe SOI layer 104 (resulting in n-doped nanowire cores, see below).Suitable n-type dopants include, but are not limited to, phosphorous andarsenic. As will be described below, doping the nanowire cores can bedone to mitigate short channel effects, especially in the case ofthicker nanowires.

According to an exemplary embodiment, the doping of the SOI layer 104 isperformed by ion implantation of dopants into the SOI layer 104 followedby an activation anneal (e.g., at a temperature of from about 600degrees Celsius (° C.) to about 1,100° C.). Other methods to dope theSOI layer 104, including (but not limited to) plasma doping or solidsource diffusion, followed with a subsequent anneal, could also be used.

As provided above, one challenge with a gate all around nanowire FETdevice architecture is the low active device width. Unlike a planardevice (where 100% of the device width contributes to active devicewidth), gate all around devices must leave some space in between thenanowires for gate materials to wrap around on the nanowires. Ashighlighted above, this decrease in active device width can becompensated for by making a stacked (multi-layer) nanowire structure.However, yielding such a structure adds significant complexity inprocessing.

As also highlighted above, another solution is to decrease the pitch ofnanowires and thus reduce the spacing between them. Still at any givenpitch, patterning larger nanowires with smaller spacing will result inlarger active device width. However, current lithography and patterninglimits make yielding large nanowires with small spacing a difficultprocess, particularly when the pitch of the nanowire is scaled down tobelow 50 nm.

Advantageously, by way of the present techniques, smaller nanowires withlarger spacing are first patterned and then an epitaxial shell is formedaround the nanowires to increase the nanowire size and at the same timereduce the spacing. This process serves to increase the active devicewidth while maintaining the nanowire pitch. See description of FIG. 11,below, describing device width, spacing and pitch. This epitaxial shellcan also optionally be doped. Therefore, any combination ofdoped/undoped core and doped/undoped shell may be employed according tothe present techniques. This is the core/shell configuration mentionedabove.

Further, as highlighted above, doping the nanowire cores can be done tomitigate short channel effects, especially in the case of thickernanowires. Namely, doping (to control short channel effects) ispreferred when thicker nanowires are used, and the nanowires may beundoped if they are thinner. By way of example only, nanowires having adiameter of from about 3 nm to about 14 nm, e.g., a diameter of fromabout 5 nm to about 10 nm, may be undoped. Nanowires with a diameter ofgreater than about 14 nm would generally benefit from core doping.

Patterning of the nanowire cores is now described. As shown in FIG. 2,standard lithography techniques are used to form a hardmask 202 whichwill be used to pattern the nanowire cores and pads in the SOI layer 104(also referred to herein as a nanowire/pad lithography hardmask). By wayof example only, hardmask 202 can be formed by blanket depositing asuitable hardmask material (e.g., a nitride material, such as siliconnitride (Si₃N₄)) over the SOI layer 104 and then patterning the hardmaskmaterial using a standard photolithography process with the footprintand location of the hardmask 202. It is notable that the use of ahardmask is being used herein merely to illustrate the presenttechniques, and that other possible configurations may be implemented byone of skill in the art. For instance, a soft mask (e.g., resist) (notshown) can instead be used to pattern the nanowire cores and pads in theSOI layer 104.

As shown in FIG. 2, the nanowire/pad hardmask has a ladder-likeconfiguration. This ladder-like configuration will be transferred to theactive layer, wherein the nanowire cores will be patterned like rungs ofa ladder interconnecting the pads (see below). The pads (and portions ofthe cores) will be used to form source and drain regions of the nanowireFET device.

An etch through the hardmask 202 is then used to form the nanowire coresand pads in the SOI 104. See FIG. 3. As provided above, the nanowirecores may be doped or undoped. Doping of the nanowire cores can serve tomitigate short channel effects, especially when thicker nanowires (e.g.,nanowires having a diameter of greater than about 14 nm) are used.

According to an exemplary embodiment, this etch is performed usingreactive ion etching (RIE). For example, this RIE step may be performedusing a fluorine-containing, e.g., CHF₃/CF₄, or bromine chemistry. Asshown in FIG. 3, the nanowire cores and pads are formed having aladder-like configuration. Namely, the pads are attached at oppositeends of the nanowire cores like the rungs of a ladder. The hardmask 202may be removed at this stage with a selective wet etch process.

The nanowire cores are then suspended over the BOX. See FIG. 4.According to an exemplary embodiment, the nanowire cores are suspendedby undercutting the BOX 102 beneath the cores using an isotropic etchingprocess. This process also laterally etches portions of the BOX 102under the pads. See FIG. 4. The isotropic etching of the BOX 102 may beperformed, for example, using a diluted hydrofluoric acid (DHF). A 100:1DHF etches about 2 nm to about 3 nm of BOX layer 102 per minute at roomtemperature.

Following the isotropic etching of the BOX 102 the nanowire cores arepreferably smoothed to give them an elliptical and in some cases acircular cross-sectional shape. The smoothing of the nanowire cores maybe performed, for example, by annealing the nanowire cores in ahydrogen-containing atmosphere. Exemplary annealing temperatures may befrom about 600° C. to about 1,000° C., and a hydrogen pressure of fromabout 600 torr to about 700 torr may be employed. Exemplary techniquesfor suspending and re-shaping nanowires may be found, for example, inU.S. Pat. No. 7,884,004, issued to Bangsaruntip et al., entitled“Maskless Process for Suspending and Thinning Nanowires,” the entirecontents of which are incorporated by reference herein. During thissmoothing process, the nanowire cores are thinned. According to oneexemplary embodiment, the nanowire cores at this stage have anelliptical cross-sectional shape with a cross-sectional diameter (e.g.,measured along a major axis of the ellipse) of from about 7 nm to about35 nm.

Optionally, the nanowire cores can be thinned further. See FIG. 5. Asdescribed in conjunction with the description of FIG. 4, the nanowirecores may be re-shaped (e.g., smoothed) to an elliptical (e.g.,circular) cross-sectional shape earlier in the process. Now, thenanowire cores may be further thinned, which also can serve to give thema smoother surface. Thinning the nanowire cores prior to the growth ofthe epitaxial shell (see below) also allows for varying ratio ofcore-to-shell thickness.

By way of example only, the nanowire cores may be further thinned atthis step using a high-temperature (e.g., from about 700° C. to about1,000° C.) oxidation of the nanowire cores followed by etching of thegrown oxide. The oxidation and etching process may be repeated multipletimes to achieve desired nanowire dimensions. According to one exemplaryembodiment, the nanowire cores at this stage after being further thinnedhave a cylindrical cross-sectional shape with a cross-sectional diameterof from about 2 nm to about 30 nm.

As provided above, the nanowires will serve as (doped or undoped) coresaround which an epitaxial shell will be formed. The epitaxial shell willserve to increase the device width/decrease the channel spacing. SeeFIG. 11, described below. It is also notable that portions of thenanowire cores/epitaxial shell surrounded by the gate stack (see below)will serve as the channels of the device, while portions of the nanowirecores/epitaxial shell extending laterally out from the gate stack will(in conjunction with the pads) serve as source and drain regions of thedevice.

The epitaxial shell is then formed around the nanowire cores. See FIG.6. As provided above, the epitaxial shell serves to increase theeffective device width, and thereby decrease the spacing betweenadjacent channels. The shell can be formed from epitaxial Si, SiGe orSiC. As shown in FIG. 6, this process will also result in epitaxial Si,SiGe or SiC being formed on the pads.

It is notable that in this step of forming the epitaxial shell aroundthe nanowire cores, it is important to prevent merging the nanowiresduring the epitaxy process, otherwise a gate all around FET cannot beformed. Namely, room is needed for the gate between the nanowires.Epitaxy growth rates have to be known well enough to avoid filling inthe nanowire to nanowire completely. Given the present teachings, one ofskill in the art would be able to ascertain the appropriate processingconditions to prevent merging of the nanowires. By way of example only,at a minimum, a distance of from about 7 nm to about 10 nm is preferablyleft between adjacent nanowires.

With this nanowire core/epitaxial shell process and structure, theconfiguration of the device can beneficially be tailored to theparticular application at hand. For instance, it may be desirable toemploy a different material for the shell than that used in the core. Byway of example only, growing an epitaxial Si shell on a SiGe core willimpart tensile strain in the channel. Tensile strain in the channel isfavorable when an n-channel nanowire FET is being formed. Alternatively,growing an epitaxial SiGe shell on a Si core will impart compressivestrain in the structure. The strain may induce buckling in the suspendednanowires. The onset for buckling depends on the nanowire length andcross-section, so proper design off the nanowire dimensions could avertbuckling. Compressive strain in the channel is favorable when ap-channel nanowire FET is being formed. Alternatively, the same materialcan be used for both the nanowire core and for the epitaxial shell.

As described above, the nanowire cores can be doped or undoped and theepitaxial shell can be doped or undoped (i.e., intrinsic Si, SiGe orSiC). To dope the epitaxial material on the pads and the epitaxialshells, a dopant may be introduced during the epitaxy step for exampleby co-flowing PH₃ or AsH₃ to obtain n-type doping or B₂H₆ to obtainp-type doping. The techniques for use of a dopant during epitaxy aregenerally known to those of skill in the art and thus are not describedfurther herein. Suitable p-type and n-type dopants were provided above.

By way of example only, a chemical vapor deposition (CVD) reactor may beused to perform the epitaxial growth. For example, for silicon epitaxy,precursors include, but are not limited to, SiCl₄, SiH₄ combined withHCL. The use of chlorine allows selective deposition of silicon only onexposed silicon. A precursor for SiGe growth may be GeH₄, which mayobtain deposition selectivity without HCL. Precursors for dopants mayinclude PH₃ or AsH₃ for n-type doping and B₂H₆ for p-type doping.Deposition temperatures may range from about 550° C. to about 1,000° C.for pure silicon deposition, and as low as 300° C. for pure Gedeposition. The epitaxy process is repeated twice when doping is used,since the pFET has to be doped with n-type dopant and the nFET withp-type dopant. Moreover, the devices that are used for pFETs need to bemasked during the epitaxy for nFETs and vice-a-versa.

According to one exemplary embodiment, when the nanowire cores aredoped, the epitaxial shells are doped with a dopant of an oppositepolarity from the nanowire cores. This doping configuration is alsoreferred to herein as “counter-doping.” Thus, when the nanowire coresare p-doped, in this example the epitaxial shells are n-doped, andvice-a-versa. Again, suitable n-type and p-type dopants were providedabove. Counter-doping serves to reduce the impact of the dopants (ifany) that can migrate from the nanowire cores into the shell.

According to an exemplary embodiment where both the nanowire cores andthe epitaxial shells are doped, the dopant concentration in theepitaxial shells is less than the dopant concentration in the nanowirecores (i.e., the shell is lightly doped). By way of example only, thenanowire cores may be doped at a concentration of from about 1×10¹⁸ cm⁻³to about 7×10¹⁸ cm⁻³ while the epitaxial shells are doped at aconcentration of from about 1×10¹⁷ cm⁻³ to about 5×10¹⁷ cm⁻³. By moreheavily doping the nanowire cores (as compared to the epitaxial shells),beneficial electrostatic short-channel effects are achieved (i.e., ifthe core was only lightly doped (e.g., at a concentration of less than1×10¹⁸ cm⁻³), then these beneficial electrostatic short-channel effectswould be lost). The steps needed to achieve a desired dopantconcentration in the nanowire cores and epitaxial shells, given theteachings presented herein, would be apparent to one of skill in theart. Counter-doping may be used both in the case where the same materialis used in the nanowire cores and the epitaxial shells and wheredifferent core and shell materials are used.

A gate stack 702 is then patterned surrounding the nanowirecores/epitaxial shells in a gate all around configuration. See FIG. 7.The portions of the nanowire cores/epitaxial shells surrounded by thegates stack will serve as channels of the device. Gate stack 702contains a dielectric (or combination of dielectrics), a first gatematerial (such as a metal(s)) and optionally a second gate material(such as a metal or doped polysilicon layer), all that surround thenanowire cores/epitaxial shells (see FIG. 8, described below).

As shown in FIG. 7, since the channels have been suspended over the BOXas described above, gate stack 702 completely surrounds at least aportion of each of the nanowire cores/epitaxial shells in a gate allaround configuration.

According to an exemplary embodiment, gate stack 702 is formed bydepositing a conformal gate dielectric film 802 such silicon dioxide(SiO₂), silicon oxynitride (SiON), hafnium oxide (HfO₂), or hafniumsilicate (or other hi-K material) around the nanowire cores/epitaxialshells. See FIG. 8 which provides a view of a cross-sectional cut (i.e.,along line A-A′) through a portion of gate stack 702. Optionally, asecond conformal gate dielectric film 804 that includes, for example,HfO₂, may be applied over gate dielectric film 802. A (first) gatematerial 806 is then deposited over the conformal gate dielectric film802 (or over optional second conformal gate dielectric film 804).According to an exemplary embodiment, the gate material 806 is aconformal metal gate film that includes, for example, tantalum nitride(TaN) or titanium nitride (TiN).

Optionally, a second gate material 808 such as doped polysilicon ormetal may then be blanket deposited onto the structure (i.e., over thegate material 806 so as to surround the nanowire cores/epitaxialshells). By way of reference to FIG. 7, hardmask 710 (e.g., a nitridehardmask, such as SiN) may then be formed on the second gate material,wherein the hardmask corresponds to a gate line of the nanowire FET.Standard patterning techniques can be used to form the hardmask 710. Thegate material(s) and dielectric(s) are then etched by directionaletching that results in straight sidewalls of the gate stack. Anisotropic lateral etch is then performed to remove residue of the gatematerials underneath nanowires, shadowed from the first directionaletching (not shown). This lateral etch process could be accomplished byRIE or a chemical wet method. After the lateral etching step, the gateline 702 is formed over the suspended nanowires.

Spacers 902 are formed on opposite sides of gate stack 702. See FIG. 9.According to an exemplary embodiment, spacers 902 are formed bydepositing a blanket dielectric film such as silicon nitride and etchingthe dielectric film from all horizontal surfaces by RIE. As shown inFIG. 9, some of the deposited spacer material can remain in the undercutregions, since the RIE in that region is blocked by the pads.

Finally, a contact material such as a silicide (formed from theepitaxial Si, SiGe or SiC) 1002 is formed on the exposed epitaxialmaterial (i.e., the epitaxial material on the pads and portions of theepitaxial shells (surrounding the nanowire cores) that extend out fromthe gate). See FIG. 10. As provided above, the pads and portions of thenanowire cores/epitaxial shells that extend out from the gate will serveas source and drain regions of the device. Examples of contact materialsinclude, but are not limited to, nickel silicide or cobalt silicide. Byway of example only, formation temperatures can be from about 400° C. toabout 600° C. Once the contact material formation is performed, cappinglayers and vias for connectivity (not shown) may be formed.

FIG. 11 is a schematic diagram illustrating effective device width,spacing between adjacent channels and channel pitch, and how by way ofthe present techniques, the effective device width is increased therebydecreasing the channel-to-channel spacing. For instance, by way ofreference to FIG. 11, it can be seen that the effective device width ofone of the nanowire cores is smaller than the device width of thenanowire core with the epitaxial shell around it. Accordingly, whenthere are channels adjacent to one another (for example as shown in FIG.11), this increased device width decreases the channel-to-channelspacing between the adjacent channels (see FIG. 11, label “Channelspacing”).

FIG. 11 also illustrates the concept of channel pitch. In the presentdescription, channel pitch is the distance measured between a same pointon each of the channels. So for example in FIG. 11, pitch is beingmeasured based on a (same) point on the outer circumference of each ofthe channels. In one exemplary embodiment, the pitch of the channels inthe completed device is from about 5 nm to about 50 nm, e.g., from about20 nm to about 40 nm. It is to be noted that the present techniques areapplicable to any channel pitch range, and those pitch ranges providedherein are merely exemplary. Advantageously, according to the presenttechniques, as provided above, the pitch of the channels in thecompleted device may be less than 20 nm, for instance, from about 5 nmto about 20 nm.

It is not however always necessary to form an epitaxial shell completelysurrounding the nanowire cores (as described above) in order to achievethe beneficial results provided herein, i.e., being able to maintaineffective device width scaling in gate all around nanowire FET devicesfollowing nanowire thinning. By way of example only, in anotherexemplary embodiment, the epitaxial shell is replaced with epitaxialsidewalls that extend outwards from the sidewalls of the nanowire cores.This too will serve to maintain effective device width scaling in gateall around nanowire FET devices following nanowire thinning. Thisalternative embodiment will be now be described by way of reference toFIGS. 12-17 which illustrate an exemplary nanowire FET device and afabrication process flow.

The starting wafer for this exemplary process flow is shown in FIG. 12A.The starting wafer includes single-crystal silicon-on-insulator (SOI)layer 1203 sandwiched between a buried nitride layer 1206 and a nitridecap 1207. The wafer also includes a buried oxide (BOX) 1202 under theburied nitride layer 1206. The substrate 1201 that hosts the film stackdescribed above may be a silicon wafer and its main purpose ismechanical support. The fabrication of such a wafer may be done by waferbonding and layer transfer as was earlier described for the SOI wafer inthe embodiment above and as further described in “Silicon-on-insulatortechnology,” J. P. Colinge, pgs. 50-51 (1997), and “Semiconductor waferbonding,” Q. Y. Tong and U. Gosele, pgs. 72-76 (1999), the contents ofboth of which are incorporated by reference herein. As will be describedbelow, the SOI layer is patterned to form a plurality of nanowires andpads. As above, the nanowires will serve as “cores” on which anepitaxial material will be formed (in this case the epitaxial materialwill be formed on the sidewalls of the nanowire cores, rather than as ashell surrounding the cores as above). Thus, the nanowires will hereinafter be referred to as nanowire cores.

FIG. 12B is a top-down diagram of the structure of FIG. 12A. Referringto FIG. 12B, the SOI layer 1203 is patterned using methods such aslithography and RIE, to form a ladder-like structure having nanowirecores 1204 and pads 1205, wherein the pads 1205 are attached to oppositeends of the nanowire cores 1204 and the nanowire cores 1204 resemble therungs of a ladder. Note that the patterning by RIE also includes theetching of the nitride cap 1207 and the buried nitride layer 1206. Thedepiction in FIG. 12A represents a cross-sectional cut through thestructure of FIG. 12B, i.e., along line A1-A2.

Referring to FIGS. 13A (cross-sectional view) and 13B (top-down view), aportion 1302 of BOX 1202 is recessed to suspend the nanowire cores 1204.The now-suspended nanowire cores will herein after be given thereference numeral 1304. As described above, the lateral etching of theburied oxide that releases the nanowires is achieved by isotropicetching of the oxide. As an example wet etching with diluted HF (DHF)provides isotropic etching of the buried oxide while being selective tosilicon and silicon nitride. FIG. 13B is a top-down diagram of thestructure of FIG. 13A. The depiction in FIG. 13A represents across-sectional cut through the structure of FIG. 13B, i.e., along lineA1-A2.

FIG. 14A shows a cross-sectional view of the suspended nanowire cores ina direction perpendicular to the nanowires (direction indicated by lineB1-B2 shown in FIG. 14B). As can be seen, sidewalls of the suspendednanowire cores 1304 are exposed while top and bottom surfaces of thesuspended nanowire cores 1304 are covered by the top the nitride cap1207 and the buried nitride layer 1206. FIG. 14B is a top-down diagramof the structure of FIG. 14A. The depiction in FIG. 14A represents across-sectional cut through the structure of FIG. 14B, i.e., along lineB1-B2.

Optionally, the exposed sidewalls of the suspended nanowire cores maynow be smoothed by annealing in hydrogen ambient. The smoothingprocessing steps for the nanowire cores were described above, and thatdescription is incorporated by reference herein. One notable differencein this embodiment as compared to the core/shell embodiment above isthat the nanowire smoothing process here will affect only the exposedsidewalls of the suspended nanowire cores since the top and bottomsurfaces of the suspended nanowire cores are covered by the top nitridecap and the buried nitride layer. Processing the sidewalls of thesuspended nanowire cores is beneficial since it reduces the nanowires'line edge roughness and the smoother sidewalls provide a better surfacefor epitaxy.

Referring now to FIGS. 15A (cross-sectional view) and 15B (top-downview) which show the device structure following a selective epitaxialgrowth (labeled “sidewall epi”) of silicon or another semiconductor thatextends (grows) the nanowire cores in the direction parallel to the BOX1302. The epitaxy which is selective with respect to non-siliconsurfaces adds semiconductor material only over exposed silicon. Nodeposition takes place over silicon nitride or silicon dioxide. Theselective epitaxy adds epi sidewall 1400 over the exposed sidewallsurfaces of nanowires 1304. Depending on the choice of growth conditionsthese epi sidewalls 1400 can terminate with (111) surfaces making thegrowth self-limiting. The preferred growth method (e.g. CVD) wasdescribed above. Similarly the epi sidewalls 1400 can be pure Si, orSiGe, and may be doped or unintentionally doped (i.e., intrinsic). FIG.15B is a top-down diagram of the structure of FIG. 15A. The depiction inFIG. 15A represents a cross-sectional cut through the structure of FIG.15B, i.e., along line B1-B2. As shown in FIG. 15B, the epitaxialsidewalls extend along each nanowire core in a plane parallel to theBOX.

An advantage of this exemplary process flow is that the top nitride capand the buried nitride layer are present during the epitaxial sidewallformation. These nitride layers can serve to anchor the nanowire coreson the top and bottom thus preventing potential agglomeration of thenanowire cores during the epi process and permitting potentially highergrowth temperatures.

Referring to FIGS. 16A (cross-sectional view) and 16B (top-down view)the top nitride cap 1207 and the buried nitride layer 1206 are removedfrom the nanowire cores by a selective etch, such as hot phosphoric acid(T=180° C.). FIG. 16B is a top-down diagram of the structure of FIG.16A. The depiction in FIG. 16A represents a cross-sectional cut throughthe structure of FIG. 16B, i.e., along line B1-B2. It is notable that,while not visible in FIG. 16B, the buried nitride is still present underthe pads. What is important here is that the buried nitride layer andthe nitride cap are removed from the nanowire cores.

FIG. 17 depicts an enlarged view of the structure of FIG. 16A followingthe conformal deposition of a gate stack (surrounding the suspendednanowire cores) which includes a gate dielectric 1720 and a gateconductor 1730. The process for fabricating the gate stack was providedabove, and that description is incorporated by reference herein. It isnotable that the shape of the gate stack formed can vary depending onthe amount of gate stack material deposited. For instance, as shown inFIG. 17, when conformal layers of gate stack materials are deposited,the gate stack can take on a faceted shape (due, for example, to thepresence of the epitaxial sidewalls on the nanowire cores).Alternatively, the faceting can be eliminated by depositing a greateramount of gate stack materials which will result in a gate stack shapethe same as that shown for example in FIG. 7, described above.

It is to be understood that the device and/or processing parametersdescribed above with regard to the nanowire core/epitaxial shellembodiment which have not been repeated here in the description of thenanowire core/epitaxial sidewalls embodiment should be considered to beincorporated by reference as if fully set forth herein. Thus, by way ofexample only, the same channel pitch specifications set forth above areintended to apply to the instant embodiment.

Although illustrative embodiments of the present invention have beendescribed herein, it is to be understood that the invention is notlimited to those precise embodiments, and that various other changes andmodifications may be made by one skilled in the art without departingfrom the scope of the invention.

What is claimed is:
 1. A method of fabricating a field effect transistor(FET) device, comprising the steps of: providing asemiconductor-on-insulator (SOI) wafer having an SOI layer over a buriedoxide (BOX); etching nanowire cores and pads in the SOI layer, whereinthe pads are attached at opposite ends of the nanowire cores in aladder-like configuration; suspending the nanowire cores over the BOX;forming epitaxial shells surrounding each of the nanowire cores; andforming a gate stack that surrounds at least a portion of each of thenanowire cores and the epitaxial shells, wherein the portions of thenanowire cores and the epitaxial shells surrounded by the gate stackserve as channels of the device, wherein the pads and portions of thenanowire cores and the epitaxial shells that extend out from the gatestack serve as source and drain regions of the device, and wherein thechannels of the device have a pitch of from about 5 nm to about 50 nm.2. The method of claim 1, wherein the channels of the device have apitch of from about 20 nm to about 40 nm.
 3. The method of claim 1,further comprising the step of: thinning the nanowire cores.
 4. Themethod of claim 1, wherein the SOI layer comprises a semiconductingmaterial selected from the group consisting of: silicon, silicongermanium and silicon carbon.
 5. The method of claim 1, wherein thenanowire cores are doped with either an n-type dopant or a p-typedopant.
 6. The method of claim 1, wherein the nanowire cores areundoped.
 7. The method of claim 1, wherein the step of thinning thenanowire cores comprises the steps of: oxidizing the nanowires to forman oxide on the nanowire cores; etching the oxide formed on the nanowirecores; and repeating the oxidizing and etching steps until a desirednanowire dimension is achieved.
 8. The method of claim 1, wherein theepitaxial shells are doped with either an n-type dopant or a p-typedopant.
 9. The method of claim 1, wherein the epitaxial shells areundoped.
 10. The method of claim 1, wherein the epitaxial shellscomprise epitaxial silicon, silicon germanium or silicon carbon.
 11. Themethod of claim 1, wherein during the step of forming the epitaxialshells surrounding each of the nanowire cores, an epitaxial material isformed on the pads, the method further comprising the step of: forming acontact material on the epitaxial material and on the portions of theepitaxial shells that extend out from the gate stack.
 12. The method ofclaim 11, wherein the contact material comprises a silicide.
 13. Themethod of claim 1, further comprising the step of: forming spacers onopposite sides of the gate stack.
 14. The method of claim 1, furthercomprising the step of: annealing the nanowire cores under conditionssufficient to smoothen the nanowires.
 15. The method of claim 14,wherein the conditions comprise a temperature of from about 600° C. toabout 1,000° C. in an atmosphere containing hydrogen.
 16. The method ofclaim 1, wherein the step of forming the gate stack comprises the stepsof: depositing a conformal gate dielectric film around the nanowirecores and the epitaxial shells; depositing a conformal metal gate filmover the conformal gate dielectric film; depositing polysilicon over theconformal metal gate film; and patterning the polysilicon, the conformalgate dielectric film and the conformal metal gate film using a hardmaskto form the gate stack.
 17. The method of claim 16, wherein theconformal gate dielectric film is selected from the group consisting of:silicon dioxide, silicon oxynitride, hafnium oxide and hafnium silicate.18. The method of claim 16, wherein the conformal metal gate film isselected from the group consisting of: tantalum nitride and titaniumnitride.
 19. A FET device, comprising: a wafer having a BOX; nanowirecores and pads attached at opposite ends of the nanowire cores in aladder-like configuration on the BOX, wherein the nanowire cores aresuspended over the BOX; epitaxial shells surrounding each of thenanowire cores; and a gate stack that surrounds at least a portion ofeach of the nanowire cores and the epitaxial shells, wherein theportions of the nanowire cores and the epitaxial shells surrounded bythe gate stack serve as channels of the device, wherein the pads andportions of the nanowire cores and the epitaxial shells that extend outfrom the gate stack serve as source and drain regions of the device, andwherein the channels of the device have a pitch of from about 5 nm toabout 50 nm.
 20. The FET device of claim 19, wherein the nanowire coresare doped with either an n-type dopant or a p-type dopant.
 21. The FETdevice of claim 19, wherein the nanowire cores are undoped.
 22. The FETdevice of claim 19, wherein the epitaxial shells are doped with eitheran n-type dopant or a p-type dopant.
 23. The FET device of claim 19,wherein the epitaxial shells are undoped.
 24. The FET device of claim19, wherein the channels of the device have a pitch of from about 20 nmto about 40 nm.